Clock recovery is defined to be the reconstruction of timing information from digital data over packet switched networks. A packet switched network comprises various interfaces and layer protocols, whereas clock synchronization is usually maintained between physical connected interfaces and not maintained end-to-end. Hence, an accurate clock mechanism must be provided for services that require end-to-end clock synchronization (e.g. CES, Voice, Video, etc.) as well as for an end-to-end transmission of accurate timing information (e.g. cellular G3 applications).
The clock recovery mechanism over packet switched networks involves two basic procedures—generation of packets at the local site and reconstruction of the clock signal at the remote side. The first procedure generates packets carrying relevant information of the source clock (at the local side). These packets are transmitted to the remote side over the packet switched network. At the second procedure, reconstruction of the clock signal is obtained from the received information at the remote side.
A major problem in trying to synchronize a clock over a non-synchronized network while achieving a high precision clock accuracy is to compensate for delay variation or, in other words, to filter out network jitter affecting arriving packets. The delay in the network is a superposition of passive and active network factors. Passive network factors, such as fiber and cable, are usually constant physical factors, wherein their variation is very small and therefore can be neglected. However, active network factors, such as switches and routers, produce delay with significant variation that must be filtered out.
Several approaches known in the art are provided for clock recovery, trying to overcome the problem caused by delay variation.
IEEE 1588 standard refers to a precision clock synchronization protocol for networked measurement and control systems. This standard defines a protocol enabling precise synchronization of clocks in measurement and control systems implemented with technologies such as network communication, local computing and distributed objects. The protocol enables heterogeneous systems that include clocks of various inherent precision, resolution and stability to synchronize. The protocol further supports system-wide synchronization accuracy in the sub-microsecond range with minimal network and local clock computing resources.
The IEEE 1588 standard was developed for test equipment that is located on the same LAN. Therefore, packets are transmitted within the same network equipment, while assuming that a one-way direction of a specific packet equals exactly half the round trip delay.
This protocol enables transmission of the time stamp from the master unit to the slave unit. The slave unit takes an individual timestamp when receiving the packet and immediately re-transmits the packet back to the master unit. The master unit measures the round trip delay, thus assuming that each direction equals half the round trip delay. Based on this value, the master unit then instructs the slave unit on how to synchronize its clock.
However, it is not necessarily correct to assume that the round trip delay is comprised of two equal timed delays, wherein the time delay from a local site to a remote site equals the time delay from the remote site to the local site. For example, in networks that are asymmetrical in their nature, e.g. HFC or point-to-multipoint Ethernet radio networks, the time delay from the central site to a remote site does not equal the time delay from a remote site to the central site. This assumption becomes even more questionable when the network utilization reaches its capacity level.
The traditional approach to filter out network jitter calculates the average delay using statistical estimation. However, the main drawback of this approach is that the statistical estimation depends on active network utilization factors, consequentially presenting unstable average delay calculations.
U.S. Pat. No. 6,363,073 discloses a circuit and method for synchronizing a service clock at a destination node with a service clock at a source node for circuit emulation service over a packet network. The method includes receiving data packets from a source node of the destination node. At the destination node, the method removes from the data packets residual time-stamp (RTS) values that were created at the source node based on information received from the service clock at the source node. RTS values are stored in memory at the destination node. The method determines a majority count and a minority count of RTS values over a period of time from the RTS values stored in memory. The method further uses the majority and minority counts to set the frequency of a service clock at the destination node for use in receiving data packets.
Yet another method for overcoming delay variation provides an adaptive clock, in which the receiver buffers incoming traffic and compares the level of the buffer with a local clock. The level of the buffer is used to control the frequency of the clock, so that the clock controlling the destination node buffer must operate at a frequency precisely matched to that of the service signal input at the source node in order to avoid buffer overflow or underflow and resulting loss of data. However, this method suffers from significant limitations revealing inaccurate results, and is therefore less efficient.
The prior art using such a method for clock recovery in a packet network include U.S. Pat. No. 6,721,328 to Nichols et al. and U.S. Pat. No. 6,400,683 to Jay. This method is further disclosed in U.S. Pat. No. 6,363,073 to Nichols.
The first Nichols patent receives data packets at a destination node. The data packets are then stored in a buffer. The data packets are read out of the buffer by using a locally generated clock. The fill level of the buffer is monitored over a first period of time. A relative maximum fill for the buffer is identified during the first period of time. Further, the relative maximum fill level is used to control the frequency of the locally generated clock so as to control the rate at which data is read out of the buffer.
The Jay patent discloses a data communication network, in which a system clock rate can be inferred at a receiver by measuring the data rate during successive periods. This information is used to adjust or adapt a receiver output clock to the inferred system clock. To adapt a receiver buffer output clock frequency to the buffer input clock frequency, the level of the buffer is periodically monitored. If the fill level is greater than an upper threshold, the output clock frequency is incremented. If the fill level is less than a lower threshold, the output clock frequency is decremented. A count is maintained of the number of successive adjustment operations performed while the fill level overflows the range bounded by the thresholds. When the fill level returns to the bounded range, a number of reverse frequency adjustments are performed, thereby reducing oscillations.
Since a high precision clock recovery over a packet switched network is crucial for applications that require high accuracy clock at remote locations, it would be desirable to provide a system and method obtaining an accurate reconstruction of the clock having the same frequency in packet networks.